1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Description of Related Art
FIG. 1 is a cross sectional view illustrating a typical LCD device. As shown in FIG. 1, the LCD device includes lower and upper substrates 2 and 4 with a liquid crystal layer 10 interposed therebetween. The lower substrate 2 has a thin film transistor “S” (TFT) as a switching element and a pixel electrode 14, and the upper substrate 4 has a color filter 8 and a common electrode 12. The pixel electrode 14 is formed over a pixel region “P” serves to apply a voltage to the liquid crystal layer 10 along with the common electrode 12, and the color filter 8 serves to implement natural colors. A sealant 6 seals an edge of the lower and upper substrate 2 and 4 to prevent leakage of the liquid crystal.
FIG. 2 is a plan view illustrating the lower array substrate of the typical LCD device. As shown in FIG. 2, the lower array substrate 2 includes gate lines 22 arranged in a transverse direction and data lines 24 arranged in a longitudinal direction perpendicular to the gate lines 22. The TFTs “S” are arranged near a crossing point of the gate and data lines 22 and 24. The pixel electrodes 14 are arranged on a region defined by the gate and data lines 22 and 24. Each of the TFTs “S” include a gate electrode 26, a source electrode 28 and the drain electrode 30. The gate electrode 26 extends from the gate line 22, and the source electrode 28 extends from the data line 24. The drain electrode 30 is electrically connected with the pixel electrode 14 through a drain contact hole 30′. Data and gate pads 21 and 23 are arranged at terminal portions of the gate and data lines 22 and 24, respectively. Storage capacitors “Cst” are formed over a portion of the gate line 22.
A process for manufacturing the LCD device described above is very complex. Particularly, the lower array substrate is manufactured through several mask processes. The process of manufacturing the lower array substrate is explained below with reference with FIGS. 3A to 3E.
FIGS. 3A to 3E are cross sectional views taken long lines III—III and III′—III′ of FIG. 2, respectively. First, as shown in FIG. 3A, a metal layer is deposited on a substrate 1 using a sputtering technique after removing alien substances and organic materials and cleaning the substrate to promote adhesion between the substrate 1 and the metal layer. Thereafter, the metal layer is patterned into a gate line 22 including a gate electrode 26 using a first mask. The gate line 22 is made of a low resistive material such as aluminum or molybdenum to lower RC delay. Pure aluminum has bad corrosion resistance and may cause a line defect due to a hillock in a subsequent process. Therefore, an aluminum alloy or two or three-layered aluminum is usually used. A portion of the gate line 22 serves as a first capacitor electrode.
As shown in FIG. 3B, a gate insulating layer 50 is deposited on the exposed surface of the substrate 1 while covering the gate line 22 and the gate electrode 26. The gate insulating layer 50 has a thickness of 3000 Å and is usually made of SiNx or SiOx. A pure amorphous silicon layer 52 and a doped amorphous silicon layer 54 are sequentially deposited on the gate insulating layer 50. Then, the amorphous silicon layer 52 and the doped amorphous silicon layer 54 are patterned into an active layer 55 and a semiconductor island 53. The doped amorphous silicon layer 54 is called an ohmic contact layer and serves to reduce contact resistance between the active layer 55 and a metal layer that will be formed in a later process.
Subsequently, as shown in FIG. 3C, a metal layer is deposited on the semiconductor layers 53 and 55 and is patterned into source and drain electrodes 28 and 30 using a third mask. The source and drain electrode 53 and 55 are usually made of chromium or a chromium alloy. At the same time as the source and drain electrodes 28 and 30 are formed, the data lines 24 are formed. A second capacitor electrode 58 is formed on the gate insulating layer 50 and overlaps a portion of the gate line 22 in order to form a storage capacitor. In other words, using the third mask, the data line 24, the source and drain electrodes 28 and 30, and the second capacitor electrode 58 are formed. Using the source and drain electrodes 28 and 30 as a mask, a portion of the ohmic contact layer 54 over the gate electrode 26 is etched. If the portion of the ohmic contact layer 54 over the gate electrode 26 is not etched, it produces undesirable electrical characteristics and poor performance of the TFT “S”. Etching the portion of the ohmic contact layer 54 over the gate electrode 26 requires special attention. This is because the etching uniformity directly affects electrical characteristics of the TFT.
As shown in FIG. 3D, a passivation film 56 is formed over the substrate 1 using the fourth mask in order to protect the active layer 55. The passivation film 56 may affect electrical characteristics of the TFT due to an unstable energy state of the active layer 55 and alien substances generated during the etching process, and therefore it is usually made of an inorganic material such as SiNx and SiO2 or an organic material such as benzocyclobutene (BCB). The passivation film 56 also requires a high light transmittance, a high humidity resistance and a high durability. The passivation film 56 includes two contact holes (the drain contact hole 30′ and a capacitor contact hole 58′).
Therefore, as shown in FIG. 3E, a transparent conducting oxide layer is deposited on the passivation film 56 and is patterned into the pixel electrode 14 using a fifth mask. The pixel electrode 14 is usually made of indium tin oxide (ITO). The pixel electrode 14 is electrically connected with the drain electrode 30 through the drain contact hole 30′ and with the second capacitor electrode 58 through the capacitor contact hole 58′.
The process for manufacturing the conventional LCD device described above includes at least five masks. Further, when the gate electrode is made of aluminum, at least two masks are required to overcome an occurrence of the hillock that may be generated on the surface of the aluminum layer. Therefore, manufacturing the TFT array substrate basically requires five or six masks. Such a mask process includes various processes such as cleaning, depositing, baking, etching and the like. Therefore, even a reduction of one mask results in a shorter processing time, low production costs and high manufacturing yields.
For the foregoing reasons, there is a need for a liquid crystal display device manufactured by the mask process wherein the number of masks required is decreased.